The present invention relates to controlling the back bias on a functional circuit to reduce power consumption by the functional circuit while maintaining switching speed of the transistors at levels sufficient to satisfy system requirements. More particularly, the present invention relates to biasing a MOS integrated circuit through a closed loop circuit configured to measure a time delay created by a delay circuit, and to generate a back bias voltage dependent on the time delay.
Although reduction in power consumption has been an ongoing goal in the field of electronics, the proliferation of portable and space based CMOS devices and microprocessor driven apparatuses has created an ever growing need for power conservation, giving rise to a variety of processes and apparatuses for reducing power consumption within personal computers, including a reduction of power within integrated MOS circuits. Power consumption of a digital circuit equals dynamic power consumption plus static power consumption. This relationship can be represented by the formula:
power≈fCVDD2+(VDD)(IDC)xe2x80x83xe2x80x831)
where f is the operating frequency, C is the equivalent capacitance of the circuit, and IDC is the static current. Because it has long been recognized that dynamic power consumption is proportional to VDD2, it has been similarly understood that a reduction in supply voltage can dramatically reduce power consumption, as illustrated in a paper by von Kaenel, Macken and Degrauwe entitled xe2x80x9cA Voltage Reduction Technique for Battery-Operated Systemsxe2x80x9d in the IEEE Journal of Solid-State Circuits, Vol. 25, No. 5, October 1990, pages 1136-1140. A reduction of the supply voltage, however, has the unwanted effect of delaying the switching of the transistors within an integrated circuit, thereby slowing down the critical path of the circuit. If the circuit through-put is slowed below a certain minimum threshold, an integrated circuit can no longer function reliably in the environment for which it was designed.
An alternative approach for reducing power consumption is to raise the threshold voltage of a transistor, typically by a process known as xe2x80x9cback biasingxe2x80x9d the transistor substrate. FIG. 1 illustrates an n-channel MOS field effect transistor 100 with a xe2x80x9cbody biasxe2x80x9d or xe2x80x9cback biasxe2x80x9d voltage 104 applied to the substrate 102. Increasing the threshold voltage has the desirable effect of decreasing the transistor""s leakage current, thereby reducing power consumption. As the threshold voltage is raised, power consumption is reduced, but the switching speed of the transistor is also slowed. Once again, if the switching time of a transistor becomes excessive, the delay will render the circuit inoperative for the environment in which it is intended to function. To maximize the efficiency in terms of power consumption, designs have been proposed wherein the threshold voltage could be raised such that the circuit speed is just fast enough to satisfy system requirements. A fundamental challenge to this design goal is the fact that, although a transistor threshold is typically fixed when the circuit is manufactured, the threshold voltage will typically vary from chip to chip as a result of manufacturing tolerances. More significantly, a circuit degrades over time, typically from heat and radiation. This degradation affects a variety of functional parameters such as the threshold switching voltage and the switching speed of the transistor. Accordingly, if the threshold voltage is set as high as allowable at the time of manufacture to minimize power consumption, as soon as the transistor speed degrades at all, the transistor will be too slow to satisfy system requirements. Alternatively, if the bias is set such that it allows for a certain degradation of switching speed before the transistor falls below the acceptable lower limit, the power consumption is higher than necessary for much of the life of the transistor.
One solution has been to set the body bias as high as allowable, and lower the bias voltage over the life of the transistor as the transistor slows. To achieve this, however, the circuit must include some means of monitoring or estimating the switching speed of the transistors within a circuit to ensure that the speed remains within system requirements. Earlier methods utilizing a back biasing voltage for power reduction have typically used a single reference transistor selected from among the many transistors comprising a MOS integrated circuit. However, if the gradual degradation of the reference transistor did not exactly match the average degradation of the circuit, the technique was inaccurate. Additionally, earlier methods taking advantage of the body bias effect have been component intensive, variously requiring a fixed reference voltage, a fixed reference current, fixed resistors creating a voltage divider for use as a reference voltage, variable frequency clocks, op-amps, and multiple memory registers for storing data defining various voltage levels for application to a back-bias voltage. These various approaches can be seen in a variety of works, including U.S. Pat. No. 3,609,414 to Pleshko et al. entitled xe2x80x9cApparatus for Stabilizing Field Effect Transistor Thresholds,xe2x80x9d U.S. Pat. No. 4,142,114 to Green, U.S. Pat. No. 4,670,670 to Shoji, U.S. Pat. No. 5,682,118 to Kaenel et al., U.S. Pat. No. 5,744,996 to Kxc3x6tzle et al., the above referenced paper by von Kaenel, Macken and Degrauwe, a related paper by Gutnik and Chandraksan entitled xe2x80x9cEmbedded Power Supply for Low-Power DSP,xe2x80x9d and a paper entitled xe2x80x9cA Delay Distribution Squeezing Scheme with Speed-Adaptive Threshold-Voltage CMOS (SA-Vt CMOS) for Low Voltage LSIsxe2x80x9d by Mizuno and Ishibashi, which was presented at the 1998 International Symposium on Low Power Electronics and Design.
There exists therefore a need for a method and apparatus for reducing the power consumption of a CMOS circuit by controlling the back bias voltage applied to a CMOS circuit. There is a further need for a method and apparatus for reducing the power consumption of a CMOS circuit while monitoring the switching speed of the transistors. There is a further need for a method and apparatus for automatically adjusting the back-bias voltage to insure that the CMOS switching speed does not fall below a certain threshold level. There is also a need for a method and apparatus for controlling the back bias voltage over the life of a circuit that is not dependent on a single reference transistor. There is a further need for a method and apparatus for adjusting a back-bias voltage to reduce power consumption which avoids the addition of excessive ancillary components such as fixed reference voltage sources, fixed current sources, fixed resistors forming voltage dividers for reference voltages, variable speed clocks, op-amps, divide-by-N clock-counters, or multiple memory locations storing data defining various voltage levels for application to a back-bias voltage.
The present invention is a method of and apparatus for reducing the power consumption of a CMOS circuit by controlling the back bias voltage applied to a CMOS circuit. The present invention further provides a method of and apparatus for reducing the power consumption of a CMOS circuit while monitoring the switching speed of the transistors. The present invention further discloses a method of and apparatus for automatically adjusting the back-bias voltage to insure that the CMOS switching speed does not fall below system requirements. The present invention further discloses a method of and apparatus for adjusting a back-bias voltage to reduce power consumption while limiting the addition of excessive ancillary components such as fixed reference voltage sources, fixed current sources, fixed resistors forming voltage dividers for reference voltages, variable speed clocks, op-amps, divide-by-N counters and multiple memory locations for storing data defining various voltage levels for application to a back-bias voltage.
An apparatus for regulating a back bias voltage in a functional circuit comprises a closed loop voltage regulator having a charge pump including a charge pump input and a charge pump output, and a delay element including a delay element input, a delay element output, and a delay element body, wherein the delay element body is coupled to the charge pump output. A functional circuit with a body is coupled to the charge pump output such that a charge pump output voltage produced at the charge pump output controls a body bias on the delay element and on the functional circuit. The charge pump output voltage is dependent upon a duty cycle of a control pulse received at the charge pump input. A logic element having a logic element output is coupled to the charge pump input. The logic element further comprises a first logic input coupled to a clock pulse, and a second logic input coupled to the delay element output. The functional circuit comprises a functional circuit input. The clock pulse is advantageously coupled to the delay element input and to the functional circuit input. According to an embodiment of the invention, the logic element is an AND gate. The delay element advantageously comprises a plurality of logical inverters coupled in series. The functional circuit advantageously comprises a CMOS circuit comprising a substrate, wherein the substrate comprises the body of the functional circuit. According to one embodiment, the charge pump output is coupled directly to the substrate of the functional circuit. According to an alternative embodiment, the charge pump output is coupled to the substrate through a proportional element, wherein the back bias voltage applied to the substrate is proportional to the charge pump output voltage.
The delay element and the functional circuit are comprised of materials configured to degrade in performance at a substantially identical rate over time. The charge pump is advantageously comprised of a plurality of pumping stages, wherein a pumping stage comprises a transistor having a gate coupled to a capacitor. According to an embodiment of the present invention, a transistor within a pumping stage exhibits a threshold voltage of less than 110 mV.
A method for regulating a back bias voltage on a functional circuit comprises controlling a duty cycle of a control signal, adjusting an output voltage of a charge pump according to the duty cycle of the control signal, and applying the back bias voltage to the functional circuit, wherein the back bias voltage is related to the output voltage of the charge pump. The step of controlling a duty cycle advantageously comprises the steps of receiving the clock pulse into an input of a delay element, receiving the clock pulse into a first input of a logic element, and receiving an output signal generated at an output of the delay element into a second input of the logic element. According to a preferred embodiment, the logic element is an AND gate. The control signal is generated by the logic element. An output of the logic element is coupled to an input of a charge pump. The delay element and the functional circuit are comprised of materials configured to degrade at a substantially identical rate over time. The charge pump is advantageously comprised of a plurality of pumping stages, a pumping stage comprising a transistor having a gate coupled to a capacitor. According to an embodiment, the delay element comprises a plurality of logical inverters coupled in series.
A functional CMOS circuit comprises a plurality of transistors while maintaining a switching time of the plurality of transistors within an optimum range. A method of reducing power consumption within the functional CMOS circuit comprises the steps of altering a duty cycle of a control-pulse, regulating a back-bias voltage according to the duty-cycle of the control-pulse, and applying the back-bias voltage to the functional CMOS circuit. The control-pulse is advantageously formed at an output of an AND gate. The step of altering the duty cycle of the control-pulse comprises the steps of transmitting a clock input signal into a first input of the AND gate, delaying the clock input signal through a delay element to form a delayed clock signal, and transmitting the delayed clock signal to a second input of the AND gate. The output of the AND gate is coupled to an input of a charge pump. The back bias voltage is proportional to an output voltage of the charge pump. The back-bias voltage is applied to the delay element.
An apparatus for regulating a back bias voltage in a functional circuit comprises means for comparing a clock signal and a delay clock signal, wherein the means for comparing produces a control pulse output, means for producing a controllable DC bias voltage according to a duty cycle of the control pulse output, means for delaying having an input coupled to the clock signal, wherein an output of the means for delaying forms the delay clock signal, and wherein the DC bias voltage is coupled to a body of the means for delaying, and means for performing a digital function, wherein a body of the means for performing is coupled to the DC bias voltage. According to an embodiment, the means for comparing is an AND gate. The same clock signal compared in the means for comparing is advantageously coupled to the means for performing a digital function. The means for delaying comprises a plurality of logical inverters coupled in series, and the means for performing a digital function comprises a CMOS circuit. The means for delaying and the means for performing a digital function are comprised of materials configured to degrade in performance at a substantially identical rate over time. According to an embodiment, the means for producing a controllable DC bias voltage comprises a plurality of pumping stages, a pumping stage comprising a transistor having a gate coupled to a capacitor.